In the technical field of semiconductor devices, higher speed, higher integration density and lower power consumption LSIs or memories are in great demand for realizing ubiquitous networks and wearable portable devices. Therefore, the generational changes in design rules are becoming increasingly accelerated (e.g., International Technology Roadmap for Semiconductor: ITRS, 1999).
Semiconductor devices with an SOI (Silicon on Insulator) structure are considered to be advantageous in the further miniaturizing LSIs, etc. LOCOS (Local Oxidation of Silicon) has been known as an isolation process for the SOI-type semiconductor devices, however, recently, STI (Shallow Trench Isolation) is often used. Examples of the isolation process are disclosed in Japanese Unexamined Patent Publication Nos. 1997-199730, 1998-150204, 2000-82813, etc.
FIGS. 14(a) and (b) are cross sectional views showing an example of a prior-art semiconductor device in which STI was used for the isolation. FIG. 14(b) is a cross sectional view taken at line D—D in FIG. 14(a).
The semiconductor device has a semiconductor layer 53 formed on the upper surface of a silicon substrate 51 via a buried oxide film 52. The semiconductor layer 53 is configured by laminating a first Si film 54, an SiGe film 55, and a second Si film 56 in this order. The semiconductor layer 53 is shaped like an island with a trench formed by STI, and has a source-drain region 57, a channel region 58, and a body region 59. A gate electrode 61 is formed on the channel region 58 via a gate insulation film 60. Sidewalls 62 are formed at the sides of the gate electrode 61.
Sidewalls of the semiconductor layer 53 are covered by sidewall oxide films 63, and an isolation film 64 is formed on the whole surface of the silicon substrate 51 including the inside of the formed trench. On the isolation film 64, metal wirings 65a, 65b, 65c, and 65d are formed, and are connected to the source-drain region 57, the source-drain region 57, the gate electrode 61 and the body region 59 via contacts 66a, 66b, 66c, and 66d respectively.
In the well-known isolation process using STI, the thickness of the isolation film 64 buried in the trench is reduced by the subsequent wet etching process for removing the oxide film, and as a result, the gate electrode 61 occasionally covers a corner C of the semiconductor layer 53 as shown in FIG. 14(b). Such a state causes an electric field concentration at an isolation edge, and thus threshold voltage drops and leakage current is prone to occur.
It has been suggested that electric field concentration at the isolation edge caused by STI can be avoided by thermally oxidizing the corner C at an elevated temperature of 900° C. or more. However, the elevated temperature causes a lattice relaxation, resulting in dislocation, for example, in the case of silicon germanium (SiGe), which has attracted attention recently. Thus, such a method cannot effectively suppress the electric field concentration.